1. Field of the Invention
The present invention relates to a high-density packaging technique for a semiconductor device.
2. Explanation of the Related Art
Various information devices, including large-sized computers, personal computers and portable devices, have been becoming higher in performance and smaller in size year by year. Consequently, semiconductor elements and semiconductor chips mounted on those devices are also becoming larger in size and their mounting space is becoming smaller. Under the circumstances, there has been a strong market demand for high-density packaging to mount many semiconductor chips on a limited space. To meet this demand, there has been developed a technique of mounting plural semiconductor chips in a stacked state and in association with this technique there has been developed a packaging method which uses through-silicon via electrodes for mutual connection of chips.
For example, a technique which uses hollow electrodes as through-silicon via electrodes for stacking chips is disclosed in Japanese Patent Laid-Open No. 2000-260933, Japanese Patent Laid-Open No. 2001-94041, Japanese Patent Laid-Open No. 2005-340389 and Japanese Patent Laid-Open No. 2007-53149. For connection between stacked semiconductor chips there are used thin metal wires in Japanese Patent Laid-Open No. 2000-260933, solder balls in Japanese Patent Laid-Open No. 2001-94041, and gold stud bumps in Japanese Patent Laid-Open Nos. 2005-340389 and 2007-53149. As a connecting method other than the method using through-silicon via electrodes there also has been developed a connecting method using cored solder balls, which is disclosed in Japanese Patent Laid-Open No. 2007-305774.
In connection with semiconductor devices wherein semiconductor chips are mounted in a stacked state, there is a recent tendency to thinning and reduction in size of semiconductor chips in order to improve the packaging density. However, if a semiconductor chip is thinned to a thickness of, say, 100 μm or smaller, warpage of the semiconductor chip before stacking becomes large. Consequently, in the case of stacking plural semiconductor chips, the assembling accuracy decreases, with a consequent fear of occurrence of defective connection in an early stage of assembly and lowering in connection reliability in a working environment. Further, in the case of using reduced-size semiconductor chips of about 1 to 10 mm square, it is difficult to effect positioning of the semiconductor chips with respect to each other at the time of assembly.
According to the above conventional techniques, if there are used coreless solder balls when the temperature is raised while imparting an urging load to the semiconductor chip to correct warpage, molten solder is crushed by the urging load, with the result that not only it is difficult to control the connection height but also, in the case where there is a temperature distribution within the semiconductor device, the solder melting time differs among connections and hence there occurs tilting of the semiconductor chip.
It is an object of the present invention to solve the above-mentioned problems and provide a semiconductor device wherein the connection height control between semiconductor chips and the alignment in the chip surface direction are easy even in the case of the semiconductor chips being thin and large in warpage and which is high in both assembling accuracy and reliability.